1. Field of the Invention
The present invention relates to electronic fuses (e-fuses). More specifically, the present invention relates to redundant via structures for metal fuse applications.
2. Description of the Related Art
In advanced technologies, e-fuses have been implemented at the polycrystalline silicon (PC) level. During programming, a high current pulse of short duration is passed through the structure. This irreversibly migrates silicide on top of the PC, causing a change in resistance and thus acting as a programmable fuse.
As scaling progresses, it is becoming harder to implement these e-fuses at the PC level due to drop in maximum allowable currents through the first metal layer or conductor. Also, the collateral damage associated with the event is becoming more difficult to contain. Further, the application of high-k metal gate (HMG) in the front end of the line (FEOL) prevents the use of PC fuses. As a result, there is a drive to implement these fuses at the metal interconnect levels in back end of the line (BEOL) and use the phenomenon of electromigration (EM) to program fuses. Current BEOL e-fuse structures are typically single via or a multi-level stack via structure. The void formation is unpredictable and the program current can be high.
The power requirements to cause EM in copper (Cu) interconnects are much larger than the typical PC level fuses. This is partly due to the fact that the liner materials used in Cu interconnects, such as tantalum (Ta) and tantalum nitride (TaN), must be blown along with the Cu in order to achieve proper fuse programming. Hence, there is a need to devise fuse structures that are susceptible to EM without compromising the reliability of the remaining interconnects.
In a conventional metal fuse approach, as shown in FIG. 1, a two-level structure is used. The two-level structure comprises conductor 111 embedded in dielectric layer 110, and via 121 and line 122 embedded in dielectric layer 120. A cap layer 123 is typically deposited over line 122 and dielectric layer 120. A cap layer 113 is typically deposited over dielectric layer 110 and conductor 111 as well. Electron flow is from via 121 into line 122. A high current is applied between the positive current connect (I+) and negative current connection (I−) to induce EM failure. Voltage across the structure is measured using the positive (V+) and negative (V−) voltage connections. The electron flow through the fuse structure is from the lower level metal, conductor 111, to the upper level metal, line 122.
With this design, some of the failures occur in via 121 while other failures occur in line 122, resulting in a lack of control over the failure location and leading to variability in the final resistance of the fuse structure after programming. Moreover, it is not possible to electrically determine whether the failure is in via 121 or line 122. Failures in line 122 are less desirable because cap layer 123 may be compromised during the programming process.
The programming process with this design may lead to damage in the surrounding dielectric layer 120. It is likely that material from the blown fuse area will be present in the damaged dielectric region. If this is the case, then there is concern that the material will migrate throughout the dielectric, causing a short circuit to neighboring lines.
Due to the nature of the liner deposition process, liner 124 coverage in via 121 depends on which via sidewall is being covered. In the case of Ta and TaN, a physical vapor deposition (PVD) process is used such that the line feature above via 121 will affect the liner coverage in the via. The same holds for the Cu seed that is deposited by PVD following liner deposition. As shown in FIG. 1, poor liner coverage occurs on via sidewall 125, opposite to the end of the line above, while good liner coverage occurs on via sidewall 126. This is a result of a dielectric shadowing effect in which the presence of a line end prevents liner material from adequately coating the opposite via sidewall. This represents a less than ideal situation because vias with good liner coverage will require higher power to be blown. The failures in the line are less desirable because cap layer 123, such as silicon nitride (Si3N4) or silicon carbide (SiC) may be compromised during the programming process. Finally, the programming process will lead to damage in the surrounding dielectric region. It is likely that material from the blown fuse area will be present in the damaged dielectric region. In this situation, there is a concern that the material will migrate throughout the dielectric, causing a short circuit to neighboring lines.
In order to cause more failures in the via, a stacked via metal fuse structure can be also used, as shown in FIG. 2. The three level structure comprises conductor 211 embedded in dielectric layer 210, and via 221 and line 222 embedded in dielectric layer 220. A cap layer 213 is typically deposited over dielectric layer 210 and conductor 211 as well as cap layer 223 over dielectric layer 220 and line 222. The structure further comprises via 231 and line 232 embedded in dielectric layer 230 and electrically connected to line 222. A cap layer 233 is typically deposited over line 232 and dielectric layer 230. Electron flow is from via 231 into line 232. Here, failures are more likely to occur in the vias than in metal line 232 due to the presence of both via 221 and via 231. However, such a structure still has the possibility of line failures.
Therefore, a structure is needed such that failure locations are better controlled.